1) Field of Invention
The invention relates to methods of forming high-density Metal/polysilicon Oxide Nitride Oxide Silicon (MONOS) memory arrays and the resulting high density MONOS memory arrays.
2) Description of Prior Art
Floating gate and MONOS are two types of non-volatile memories. In conventional floating gate structures, electrons are stored onto a floating gate, by either F-N tunneling or source side injection. Conventional MONOS devices store electrons usually by direct tunneling in the Oxide-Nitride-Oxide (ONO) layer which is below the memory word gate. Electrons are trapped in the Nitride layer of the ONO composite. The MONOS transistor requires one less polysilicon layer than the floating gate device, which simplifies the process and could result in a denser array.
MONOS structures are conventionally planar devices in which an ONO composite layer is deposited beneath the word gate. The thickness of the bottom oxide of the ONO layer is required be less than 3.6 nm, in order to utilize direct tunneling for program operations. However in 1998, a MONOS structure with a bottom oxide thickness of 5.0 nm, and side wall polysilicon gates and source side injection program was first reported by Kuo-Tung Chang et al, in, xe2x80x9cA New SONOS Memory Using Source Side Injection for Programmingxe2x80x9d, IEEE Electron Letters, Vol. 19, No. 7, July 1998. In this structure, as shown in FIG. 1, a side wall spacer 20 is formed on one side of the word gate by a typical side wall process, and the ONO composite 22 is underneath the side wall gate, instead of under the word gate as for conventional MONOS memory cells. The channel under the SONOS side wall control gate is larger than 100 nm, so the program mechanism is source side injection, which is faster and requires lower voltages than electron tunneling, despite the thicker bottom oxide. During source side injection, a channel potential is formed at the gap between the side wall gate and the select/word gate. Channel electrons 30 are accelerated in this gap region and become hot enough to inject into the ONO layer. Thus Kuo-Tung Chang""s SONOS memory is able to achieve better program performance than previous direct tunneling MONOS cells.
While the SONOS memory cell is unique among MONOS memories for its split gate structure and source side injection program, its structure and principles of program are similar to those for a conventional split gate floating gate device. Both cell types have a word gate and side wall spacer gate in series. The most significant differences lie in the manner of side wall gates utilization and electron storage regions. In the split gate floating gate cell, the side wall spacer is a floating gate onto which electrons are stored. The floating gate voltage is determined by capacitance coupling between the word gate, diffusion, and floating gate. For the SONOS cell, electrons are stored in the nitride region beneath the side wall spacer, which is called the control gate. The nitride region voltage is directly controlled by the voltage of the above side wall gate.
A floating gate memory cell having faster program and higher density was introduced in co-pending U.S. patent application Ser. No. 09/313,302 to the same inventors, filed on May 17, 1999. FIG. 3A is an array schematic and FIG. 3B is a layout cross-section of this fast program, dual-bit, and high density memory cell. In this memory structure, high density is achieved by pairing two side wall floating gates to one word gate (for example, floating gates 312 and 313 and word gate 341), and sharing interchangeable source-drain diffusions (321 and 322) between cells. Thus a single memory cell has two sites of electron storage. Additional polysilicon lines xe2x80x9ccontrol gatesxe2x80x9d run in parallel to the diffusions and orthogonal to the word gates. The control gates (331 and 332) couple to the floating gates and provide another dimension of control in order to individually select a floating gate from its pair. This memory is further characterized by fast programming due to ballistic injection. Using the same device structure, if the side wall gate channel is reduced to less than 40 nm with proper impurity profiles, the injection mechanism changes from source side injection to a new and much more efficient injection mechanism called ballistic injection. The ballistic injection mechanism has been proven by S. Ogura in xe2x80x9cStep Split Gate Cell with Ballistic Direction Injection for EEPROM/Flashxe2x80x9d, IEDM 1998, pp. 987. In FIG. 2A, results between ballistic injection (line 25) and conventional source side injection (line 27) are compared for a floating gate memory cell. Although the structures are very similar, when the control gate is 100 nm, the injection mechanism is source side injection. However, as illustrated in FIG. 2B, when the channel is reduced to 40 nm to satisfy the short channel length requirement for ballistic injection (line 35), program speed increases by three orders of magnitude under the same bias conditions, or at half of the floating gate voltage requirement for source side injection (line 37).
In contrast, the side wall channel length of Kuo Tung Chang""s SONOS memory structure is 200 nm, so the program mechanism is source side injection. Thus there is a significant dependence between the short channel length and the injection mechanism.
In this invention, a fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is achieved with a two or three polysilicon split gate side wall process. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection (S. Ogura) which provides high electron injection efficiency and very fast program at low program voltages of 3xcx9c5V. The cell structure is realized by (i) placing side wall control gates over a composite of Oxide-Nitride-Oxide (ONO) on both sides of the word gate, and (ii) forming the control gates and bit diffusion by self-alignment and sharing the control gates and bit diffusions between memory cells for high density. Key elements used in this process are:
(i) Disposable side wall process to fabricate the ultra short channel and the side wall control gate with or without-a step structure.
(ii) Self-aligned definition of the control gate over the storage nitride and the bit line diffusion, which also runs in the same direction as the control gate.
The features of fast program, low voltage, ultra-high density, dual-bit, multi-level MONOS NVRAM Of the present invention include:
1. Electron memory storage in nitride regions within an ONO layer underlying the control gates.
2. High density dual-bit cell in which there are two nitride memory storage elements per cell
3. High density dual-bit cell can store multi-levels in each of the nitride regions
4. Low current program controlled by the word gate and control gate
5. Fast, low voltage program by ballistic injection utilizing the controllable ultra-short channel MONOS
6. Side wall control poly gates to program and read multi-levels while masking out memory storage state effects of the unselected adjacent nitride regions and memory cells.
The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and {fraction (1/2)} a source diffusion and xc2xd a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.
A summary of the operating conditions for multi-level storage is given in FIG. 7C. During read, the following conditions need to be met: the voltage of the unselected control gate within a selected memory cell must be greater than the threshold voltage of the control+source voltage. The word select gate in the control gate pair is raised to the threshold voltage of the word gate+an override delta of around 0.5V+source voltage (Vtxe2x88x92wl+Voverdrive+Vs). Un-selected MONOS cells will be disabled by reducing the associated control gates to 0V. Program conditions are: Word line voltage is greater than threshold+an overdrive voltage delta for low current program. Both control gates in the selected pair are greater than Vt-high (the highest threshold voltage within the range of multi-level thresholds)+override delta. Adjacent memory cells sharing the same word line voltage are disabled by adjusting the control gates only.